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d a t a sh eet product speci?cation supersedes data of march 1994 file under integrated circuits, ic06 1999 jan 11 integrated circuits 74hct9046a pll with bandgap controlled vco
1999 jan 11 2 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a features low power consumption centre frequency up to 17 mhz (typ.) at v cc = 5.5 v choice of two phase comparators (1) : C exclusive-or (pc1) C edge-triggered jk flip-flop (pc2) no dead zone of pc2 charge pump output on pc2, whose current is set by an external resistor r b centre frequency tolerance 10% excellent voltage-controlled-oscillator (vco) linearity low frequency drift with supply voltage and temperature variations on chip bandgap reference glitch free operation of vco, even at very low frequencies inhibit control for on/off keying and for low standby power consumption operation power supply voltage range 4.5 to 5.5 v zero voltage offset due to op-amp buffering output capability: standard i cc category: msi. applications fm modulation and demodulation where a small centre frequency tolerance is essential frequency synthesis and multiplication where a low jitter is required (e.g. video picture-in-picture) frequency discrimination (1) r b connected between pin 15 and ground: pc2 mode, with pcp out at pin 2. pin 15 left open or connected to v cc : pc1 mode with pc1 out at pin 2. tone decoding data synchronization and conditioning voltage-to-frequency conversion motor-speed control. general description the 74hct9046a is a high-speed si-gate cmos device. it is specified in compliance with jedec standard no. 7a . quick reference data gnd = 0 v; t amb = 25 c; t r = t f 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w) a) p d = c pd v cc 2 f i + s (c l v cc 2 f o ) where: b) f i = input frequency in mhz; c l = output load capacity in pf; f o = output frequency in mhz; v cc = supply voltage in v; s (c l v cc 2 f o ) = sum of the outputs. 2. applies to the phase comparator section only (inhibit = high). for power dissipation of the vco and demodulator sections see figs 26 to 28. ordering information symbol parameter conditions typ. unit f c vco centre frequency c1 = 40 pf; r1 = 3 k w ; v cc = 5 v 16 mhz c i input capacitance 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 20 pf extended type number package pins pin position material code 74hct9046an 16 dil16 plastic sot38z 74HCT9046AD 16 so16 plastic sot109a
1999 jan 11 3 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a pinning symbol pin description gnd 1 ground (0 v) (phase comparators) pc1 out / pcp out 2 phase comparator 1 output/phase comparator pulse output comp in 3 comparator input vco out 4 vco output inh 5 inhibit input c1 a 6 capacitor c1 connection a c1 b 7 capacitor c1 connection b gnd 8 ground (0 v) (vco) vco in 9 vco input dem out 10 demodulator output r1 11 resistor r1 connection r2 12 resistor r2 connection pc2 out 13 phase comparator 2 output (current source adjustable with r b ) sig in 14 signal input r b 15 bias resistor (r b ) connection v cc 16 supply voltage fig.1 pin configuration. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd pc1 / out pcp out comp in vco out c1 a c1 b gnd vco in dem out r2 r1 pc2 out sig in v cc r 9046a mbd037 - 1 inh b logic/functional symbols and diagrams fig.2 logic symbol. mbd038 - 1 pc1 / out vco out c1 a c1 b vco in dem out r2 r1 sig in inh vco 6 7 11 12 9 5 4 10 2 13 3 14 15 pc2 out f comp in r b pcp out fig.3 iec logic symbol. mbd039 - 1 sig in inh 6 7 11 12 9 5 4 10 2 13 3 14 15 f comp in pll 9046a pc1 / out vco out c1 a c1 b vco in dem out r2 r1 pc2 out r b pcp out
1999 jan 11 4 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.4 functional diagram. phase comparator 2 13 phase comparator 1 2 15 sig in comp in c1 a c1 b dem out inh vco in r2 12 11 314 4 7 6 5109 c1 9046a vco r s r1 r4 r3 c2 pc2 out mbd040 - 1 pc1 / out vco out r2 r1 r b pcp out r b
1999 jan 11 5 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... mbd102 - 1 pcp dq cp q r d logic 1 dq cp q r d logic 1 down up charge pump v ref2 pc1 / out out pcp out pc2 r b r b c2 r4 2 13 r3 15 comp in sig in 314 pc1 v ref2 v ref1 band gap 5 inh 9 in v ref2 vco dem out vco out c1 b c1 a 7 64 c1 v ref1 12 r2 11 r1 10 r f out f in r2 r1 s vco fig.5 logic diagram.
1999 jan 11 6 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a functional description the 74hct9046a is a phase-locked-loop circuit that comprises a linear vco and two different phase comparators (pc1 and pc2) with a common signal input amplifier and a common comparator input (see fig.4). the signal input can be directly coupled to large voltage signals (cmos level), or indirectly coupled (with a series capacitor) to small voltage signals. a self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. with a passive low-pass filter, the '9046a' forms a second-order loop pll. the principle of this phase-locked-loop is based on the familiar hct4046a. however extra features are built in, allowing very high performance phase-locked-loop applications. this is done, at the expense of pc3, which is skipped in this hct9046a. the pc2 is equipped with a current source output stage here. further a bandgap is applied for all internal references, allowing a small centre frequency tolerance. the details are summed up in the next section called: differences with respect to the familiar hct4046a. if one is familiar with the hct4046a already, it will do to read this section only. differences with respect to the familiar hct4046a a centre frequency tolerance of maximum 10%. the on board bandgap sets the internal references resulting in a minimal frequency shift at supply voltage variations and temperature variations. the value of the frequency offset is determined by an internal reference voltage of 2.5 v instead of v cc - 0.7 v. in this way the offset frequency will not shift over the supply voltage range. a current switch charge pump output on pc2 allows a virtually ideal performance of pc2. the gain of pc2 is independent of the voltage across the low-pass filter. further a passive low-pass filter in the loop achieves an active performance now. the influence of the parasitic capacitance of the pc2 output plays no role here, resulting in a true correspondence of the output correction pulse and the phase difference even up to phase differences as small as a few nanoseconds. because of its linear performance without dead zone, higher impedance values for the filter, hence lower c-values, can now be chosen. correct operation will not be influenced by parasitic capacitances as in the instance with voltage source output of the 4046a. no pc3 on pin 15 but instead a resistor connected to gnd, which sets the load/unload currents of the charge pump (pc2). extra gnd pin at pin 1 to allow an excellent fm demodulator performance even at 10 mhz and higher. combined function of pin 2. if pin 15 is connected to v cc (no bias resistor r b ) pin 2 has its familiar function viz. output of pc1. if at pin 15 a resistor (r b ) is connected to gnd it is assumed that pc2 has been chosen as phase comparator. connection of r b is sensed by internal circuitry and this changes the function of pin 2 into a lock detect output (pcp out ) with the same characteristics as pcp out of pin 1 of the well known 74hct4046a. the inhibit function differs. for the hct4046a a high level at the inhibit input (inh) disables the vco and demodulator, while a low level turns both on. for the 74hct9046a a high level on the inhibit input disables the whole circuit to minimize standby power consumption. vco the vco requires one external capacitor c1 (between c1 a and c1 b ) and one external resistor r1 (between r1 and gnd) or two external resistors r1 and r2 (between r1 and gnd, and r2 and gnd). resistor r1 and capacitor c1 determine the frequency range of the vco. resistor r2 enables the vco to have a frequency offset if required (see fig.5). the high input impedance of the vco simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. in order not to load the low-pass filter, a demodulator output of the vco input voltage is provided at pin 10 (dem out ). the dem out voltage equals that of the vco input. if dem out is used, a load resistor (r s ) should be connected from pin 10 to gnd; if unused, dem out should be left open. the vco output (vco out ) can be connected directly to the comparator input (comp in ), or connected via a frequency-divider. the vco output signal has a duty factor of 50% (maximum expected deviation 1%), if the vco input is held at a constant dc level. a low level at the inhibit input (inh) enables the vco and demodulator, while a high level turns both off to minimize standby power consumption.
1999 jan 11 7 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a phase comparators the signal input (sig in ) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard hc family input logic levels. capacitive coupling is required for signals with smaller swings. p hase comparator 1 (pc1) this circuit is an exclusive-or network. the signal and comparator input frequencies (f i ) must have a 50% duty factor to obtain the maximum locking range. the transfer characteristic of pc1, assuming ripple (f r = 2f i ) is suppressed, is: where: v demout is the demodulator output at pin 10. v demout = v pc1out (via low-pass). the phase comparator gain is: the average output voltage from pc1, fed to the vco input via the low-pass filter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of signals (sig in ) and the comparator input (comp in ) as shown in fig.6. the average of v demout is equal to 1 2 v cc when there is no signal or noise at sig in and with this input the vco oscillates at the centre frequency (f c ). typical waveforms for the pc1 loop locked at f c are shown in fig.7. this figure also shows the actual waveforms across the vco capacitor at pins 6 and 7 (v c1a and v c1b ) to show the relation between these ramps and the vco out voltage. v demout v cc p ---------- - f sigin f compin C () = k p v cc p ---------- - vr () = the frequency capture range (2f c ) is defined as the frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. this configuration remains locked even with very noisy input signals. typical behaviour of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the vco centre frequency. p hase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detector. when the pll is using this comparator, the loop is controlled by positive signal transitions and the duty factors of sig in and comp in are not important. pc2 comprises two d-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of pc2. the circuit functions as an up-down counter (fig.5) where sig in causes an up-count and comp in a down count. the current switch charge pump output allows a virtually ideal performance of pc2, due to appliance of some pulse overlap of the up and down signals. see fig.8a.
1999 jan 11 8 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.6 phase comparator 1; average output voltage as a function of input phase difference. mbd101 - 1 180 o pcin 0 o 90 o 1/2v 0 v v demout(av) cc cc f v demout v pc1out v cc p ---------- - f sigin f compin C () == f pcin f sigin f compin C () = fig.7 typical waveforms for pll using phase comparator 1; loop-locked at f c . mbd100 pc1 out vco in v cc gnd vco out comp in sign in pin 6 pin 7 v c1a v c1b
1999 jan 11 9 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a the pump current i p is independent from the supply voltage and is set by the internal bandgap reference of 2.5 v. r b is the external bias resistor between pin 15 and ground. the current and voltage transfer function of pc2 are shown in fig.9. the phase comparator gain is: typical waveforms for the pc2 loop locked at f c are shown in fig.10. when the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the up output driver at pc2 out is held on for a time corresponding to the phase difference ( f pcin ). when the phase of sig in lags that of comp in , the down or sink driver is held on. when the frequency of sig in is higher than that of comp in , the source output driver is held on for most of the input signal cycle time and for the remainder of the cycle time both drivers are off (3-state). if the sig in frequency is lower than the comp in frequency, then it is the sink driver that is held on for most of the cycle. subsequently the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable point the voltage on c2 remains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. also in this condition the signal at the phase comparator pulse output (pcp out ) has a minimum output pulse width equal to the overlap time, so can be used for indicating a locked condition. i p 17 2.5 r b ------- - a () = k p i p 2 p ------- ar () = thus for pc2 no phase difference exists between sig in and comp in over the full frequency range of the vco. moreover, the power dissipation due to the low-pass filter is reduced because both output drivers are off for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. with no signal present at sig in the vco adjust, via pc2, to its lowest frequency. by using current sources as charge pump output on pc2, the dead zone or backlash time could be reduced to zero. also, the pulse widening due to the parasitic output capacitance plays no role here. this enables a linear transfer function, even in the vicinity of the zero crossing. the differences between a voltage switch charge pump and a current switch charge pump are shown in fig.11. the design of the low-pass filter is somewhat different when using current sources. the external resistor r3 is no longer present when using pc2 as phase comparator. the current source is set by r b . a simple capacitor behaves as an ideal integrator now, because the capacitor is charged by a constant current. the transfer function of the voltage switch charge pump may be used. in fact it is even more valid, because the transfer function is no longer restricted for small changes only. further the current is independent from both the supply voltage and the voltage across the filter. for one that is familiar with the low-pass filter design of the 4046a a relation may show how r b relates with a fictive series resistance, called r3'. this relation can be derived by assuming first that a voltage controlled switch pc2 of the 4046a is connected to the filter capacitance c2 via this fictive r3' (see fig.8b). then during the pc2 output pulse the charge current equals: with the initial voltage v c2(0) at: 1 2 v cc = 2.5 v, as shown before the charge current of the current switch of the 9046a is: hence: using this equivalent resistance r3' for the filter design the voltage can now be expressed as a transfer function of pc2; assuming ripple (f r =f i ) is suppressed, as: again this illustrates the supply voltage independent behaviour of pc2. examples of pc2 combined with a passive filter are shown in figs 12 and 13. figure 12 shows that pc2 with only a c2 filter behaves as a high-gain filter. for stability the damped version of fig.13 with series resistance r4 is preferred. practical design values for r b are between 25 and 250 k w with r3' = 1.5 to 15 k w for the filter design. higher values for r3' require lower values for the filter capacitance which is very advantageous at low values the loop natural frequency w n . i p v cc v c2 0 () C r3' ---------------------------------- - = i p 2.5 r3' -------- - = i p 17 2.5 r b ------- - = r3' r b 17 ------ - w () = k pc2 5 4 p ------ - vr () =
1999 jan 11 10 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mbd099 r3' i p up down c2 v cc pc2 out vc2 out fig.8 the current switch charge pump output of pc2. b. a. mbd046 - 1 pc2 out c2 v cc i p i p down up d f = f pulse overlap of approximately 15 ns pcin a. at every df , even at zero df both switches are closed simultaneously for a short period (typically 15 ns). b. comparable voltage-controlled switch. 0 msb306 - 1 20 1/2v 0 v v demout(av) cc cc p f pcin 2 p i x r p f pcin = f sigin f compin 20 p f pcin 2 p i p i p fig.9 phase comparator 2. two kinds of transfer functions may be regarded: a. the current transfer: b. the voltage transfer; this transfer can be observed at pc2 out by connecting a resistor (r = 10 k w ) between pc2 out and 1 2 v cc ; pump current i p 2 p ------- f pcin v demout v pc2out 5 4 p ------ - f pcin == b. a.
1999 jan 11 11 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mbd047 - 1 sig in comp in vco out high impedance off state, (zero current) up down current at pc2 out pc2 /vco out in pcp out opc in fig.10 timing diagram for pc2. the pulse overlap of the up and down signals (typically 15 ns). fig.11 the response of a locked-loop in the vicinity of the zero crossing of the phase error. b. response with current switch charge-pump pc2 out as applied in the hct9046a. mbd043 25 2.50 2.75 2.25 vco in 025 phase error (ns) (1) (1) (2) 25 2.50 2.75 2.25 vco in 025 phase error (ns) a. response with traditional voltage-switch charge-pump pc2 out (4046a). (1) due to parasitic capacitance on pc2 out . (2) backlash time (dead zone). b. a.
1999 jan 11 12 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a loop filter component selection mbd045 - 1 w j () f w 1/ output input c2 i p i p 17 r b 1/ t 1 a a t 1 a fig.12 simple loop filter for pc2 without damping. a. b. amplitude characteristic: c. pole zero diagram. t 1 r b 17 ------ - c2 r3' c2 == f j w () 1 1a j wt 1 + ---------------------------- - 1 j wt 1 ----------- ? = a. b. c. mbd044 - 1 w j () f m 1 / t 2 w o 1/ t 2 1/ t 1 output input r4 c2 i p i p 17 r b a 1/ t 1 a a fig.13 simple loop filter for pc2 with damping. a. b. amplitude characteristic: c. pole zero diagram. a = dc gain limit, due to leakage. t 1 r b 17 ------ - c2 r3' c2 == t 2 r4 c2 = f j w () 1j wt 2 + 1a j wt 1 + ---------------------------- - = a. b. c.
1999 jan 11 13 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a recommended operating conditions for 74hct limiting values in accordance with the absolute maximum rating system (iec 134); voltages are referenced to gnd (ground = 0 v). note 1. temperature range: - 40 to +125 c. symbol parameter conditions min. typ. max. unit v cc dc supply voltage 4.5 5.0 5.5 v v i dc input voltage 0 - v cc v v o dc output voltage 0 - v cc v t amb operating ambient temperature see dc and ac characteristics - 40 - +85 c - 40 - +125 c t r , t f input rise and fall times (pin 5) v cc = 4.5 v - 6 500 ns symbol parameter conditions min. max. unit v cc dc supply voltage - 0.5 +7 v i ik dc input diode current for v i <- 0.5 v or v i > v cc + 0.5 v - 20 ma i ok dc output diode current for v o <- 0.5 v or v o > v cc + 0.5 v - 20 ma i o dc output source or sink current for - 0.5 v < v o < v cc + 0.5 v - 25 ma i cc ; i gnd dc v cc or gnd current - 50 ma t stg storage temperature - 65 +150 c p tot total power dissipation per package note 1 plastic dil above +70 c: derate linearly with 12 mw/k - 750 mw plastic mini-pack (so) above +70 c: derate linearly with 8 mw/k - 500 mw
1999 jan 11 14 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a dc characteristics for 74hct voltages are referenced to gnd (ground = 0 v). symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) v i (v) other min. typ. max. min. max. min. max. phase comparator section v ih dc coupled high level input voltage sig in , comp in 3.15 2.4 - 3.15 - 3.15 - v 4.5 - v il dc coupled low level input voltage sig in , comp in - 2.1 1.35 - 1.35 - 1.35 v 4.5 - v oh high level output voltage pcp out , pcn out 4.4 4.5 - 4.4 - 4.4 - v 4.5 v ih or v il i o = - 20 m a 3.98 4.32 - 3.84 - 3.7 - v 4.5 v ih or v il i o = - 4.0 ma v ol low level output voltage pcp out , pcn out - 0 0.1 - 0.1 - 0.1 v 4.5 v ih or v il i o = - 20 m a - 0.15 0.26 - 0.33 - 0.4 v 4.5 v ih or v il i o = - 4.0 ma i i input leakage current sig in , comp in -- 30 - 38 - 45 m a 5.5 v cc or gnd i oz 3-state off-state current pc2 out -- 0.5 - 5.0 - 10.0 m a 5.5 v ih or v il v o = v cc or gnd r i input resistance sig in , comp in - 250 ----- k w 4.5 v i at self-bias operating point; d v i = 0.5 v; see figs 14 to 16 r b bias resistance 25 - 250 ---- k w 4.5 - i p charge pump current 0.53 1.06 2.12 ---- ma 4.5 - r b = 40 k w
1999 jan 11 15 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a vco section v ih dc coupled high level input voltage inh 2.0 1.6 - 2.0 - 2.0 - v 4.5 to 5.5 - v il dc coupled low level input voltage inh - 1.2 0.8 - 0.8 - 0.8 v 4.5 to 5.5 - v oh high level output voltage vco out 4.4 4.5 - 4.4 - 4.4 - v 4.5 v ih or v il i o = - 20 m a 3.98 4.32 - 3.84 - 3.7 - v 4.5 v ih or v il i o = - 4.0 ma v ol low level output voltage vco out - 0 0.1 - 0.1 - 0.1 v 4.5 v ih or v il i o = 20 m a - 0.15 0.26 - 0.33 - 0.4 v 4.5 v ih or v il i o = 4.0 ma v ol low level output voltage c1 a , c1 b -- 0.40 - 0.47 - 0.54 v 4.5 v ih or v il i o = 4.0 ma i i input leakage current inh and vco in -- 0.1 - 1.0 - 1.0 m a 5.5 v cc or gnd r1 resistance 3 - 300 ---- k w 4.5 - r2 resistance 3 - 300 ---- k w 4.5 - c1 capacitance 40 - no limit ---- pf 4.5 - v vcoin operating voltage range at vco in 1.1 - 3.4 ---- v 4.5 - over the range speci?ed for r1 1.1 - 3.9 ---- v 5.0 - 1.1 - 4.4 ---- v 5.5 - symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) v i (v) other min. typ. max. min. max. min. max.
1999 jan 11 16 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a note 1. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given above. to determine d i cc per input, multiply this value by the unit load coefficient shown in table 1. table 1 unit load coef?cient table. demodulator section r s resistance 50 - 300 ---- k w 4.5 - at r s > 300 k w the leakage current can in?uence v demout v off offset voltage vco in to v demout - 20 ----- mv 4.5 - v i = v vcoin = 1 2 v cc ; values taken over r s range, see fig.17 r d dynamic output resistance at dem out - 25 -----w 4.5 - v demout = 1 2 v cc quiescent supply current i cc quiescent supply current (disabled) -- 8.0 - 80.0 - 160.0 m a 5.5 - pin 5 at v cc d i cc additional quiescent supply current per input pin for unit load coef?cient is 1; note 1; v i = v cc - 2.1 v - 100 360 - 450 - 490 m a 4.5 - other inputs at v cc or gnd input unit load coefficient inh 1.00 symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) v i (v) other min. typ. max. min. max. min. max.
1999 jan 11 17 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.14 typical input resistance curve at sig in , comp in . mbd108 self-bias operating point v i d v i i i fig.15 input resistance at sig in ; comp in with d v i = 0.5 v at self-bias point. 800 600 200 0 400 mga956 - 1 v (v) i 1/2v 0.25 cc 1/2v cc 1/2v 0.25 cc r i (k ) w 5.5 v 4.5 v v = cc fig.16 input current at sig in ; comp in with d v i = 0.5 v at self-bias point. 5 5 0 mga957 v (v) i 1/2 v 0.25 cc 1/2 v cc 1/2 v 0.25 cc i i ( a) m 4.5 v 5.5 v v = cc 5.5 v 4.5 v fig.17 offset voltage at demodulator output as a function of vco in and r s . 40 40 0 mga958 v (v) 1/2 v 2 cc 1/2 v cc 1/2 v 2 cc 20 20 60 v off (mv) vcoin 5.5 v 4.5 v v = cc ___ r s = 50 k w . - - - r s = 300 k w .
1999 jan 11 18 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf. symbol parameter t amb ( c) unit test condition +25 - 40 to +85 - 40 to +125 v cc (v) waveforms min. typ. max. min. max. min. max. phase comparator section t phl /t plh propagation delay sig in , comp in to pc1 out - 23 40 - 50 - 60 ns 4.5 fig.18 t phl /t plh propagation delay sig in , comp in to pcp out - 35 68 - 85 - 102 ns 4.5 fig.18 t pzh /t pzl 3 - state output enable time sig in , comp in to pc2 out - 30 56 - 70 - 84 ns 4.5 fig.19 t phz /t plz 3 - state output enable time sig in , comp in to pc2 out - 36 65 - 81 - 98 ns 4.5 fig.19 t thl /t tlh output transition time - 715 - 19 - 22 ns 4.5 fig.18 v i(p-p) ac coupled input sensitivity (peak-to-peak value) at sign in or comp in - 15 ----- mv 4.5 f i = 1 mhz
1999 jan 11 19 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a vco section d f/t frequency stability with temperature change --- 0.06 --- %/k 4.5 v vcoin = 1 2 v cc ; recommended range: r1 = 10 k w ; r2 = 10 k w ; c1 = 1 nf; figs 20 to 22 d f c centre frequency tolerance - 10 - +10 ---- % 5.0 v vcoin = 3.9 v; r1 = 10 k w ; r2 = 10 k w ; c1 = 1 nf f c vco centre frequency (duty factor = 50%) 11.0 15.0 ----- mhz 4.5 v vcoin = 1 2 v cc ; r1 = 4.3 k w ; r2 = ; c1 = 40 pf; figs 23 and 31 d f vco vco frequency linearity - 0.4 ----- % 4.5 r1 = 100 k w ; r2 = ; c1 = 100 pf; figs 24 and 25 d vco duty factor at vco out - 50 ----- % 4.5 symbol parameter t amb ( c) unit test condition +25 - 40 to +85 - 40 to +125 v cc (v) waveforms min. typ. max. min. max. min. max.
1999 jan 11 20 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.18 waveforms showing input (sig in and comp in ) to output (pcp out and pc1 out ) propagation delays and the output transition times. mbd106 t phl t thl t plh t tlh sig , comp in in inputs pcp , pc1 , out out outputs v m (1) v m (1) (1) v m = 1 2 v cc ; v i = gnd to v cc . fig.19 waveforms showing the 3-state enable and disable times for pc2 out . mga941 t plz t pzh t phz 10% 90% t pzl sig in input comp in input pc2 out output m v (1) m v (1) m v (1) (1) v m = 1 2 v cc ; v i = gnd to v cc .
1999 jan 11 21 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a 50 0 50 150 20 10 10 20 0 mbd115 100 d f (%) 5.5 v 4.5 v v = cc t ( c) amb o fig.20 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd116 t ( c) amb 0 f (%) o 150 100 50 0 50 15 10 5 5 10 15 d 5.5 v 4.5 v v = cc a. r1 = 3 k w ; r2 = ; c1 = 100 pf. b. r1 = 10 k w ; r2 = ; c1 = 100 pf. b. a. 50 0 50 150 10 5 5 10 0 mbd124 100 d f (%) 5.5 v 4.5 v v = cc t ( c) amb o fig.21 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd117 t ( c) amb 0 f (%) o 150 100 50 0 50 20 15 10 5 10 15 d 5.5 v 4.5 v v = cc 5 a. r1 = 300 k w ; r2 = ; c1 = 100 pf. b. r1 = ; r2 = 3 k w ; c1 = 100 pf. b. a.
1999 jan 11 22 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mbd118 t ( c) amb 0 f (%) o 150 100 50 0 50 12 8 4 4 8 d 5.5 v 4.5 v v = cc fig.22 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd119 t ( c) amb 0 f (%) o 150 100 50 0 50 10 5 5 10 d 5.5 v 4.5 v v = cc a. r1 = ; r2 = 10 k w ; c1 = 100 pf. b. r1 = ; r2 = 300 k w ; c1 = 100 pf. b. a.
1999 jan 11 23 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.23 graphs showing vco frequency as a function of the vco input voltage (v vcoin ). a. r1 = 4.3 k w ; c1 = 39 pf. b. r1 = 4.3 k w ; c1 = 100 nf. c. r1 = 300 k w ; c1 = 39 pf. d. r1 = 300 k w ; c1 = 100 nf. a. b. c. d. handbook, halfpage 0246 800 600 200 0 400 mbd120 - 1 v (v) vcoin f vco (khz) v = 5.5 v cc 4.5 v handbook, halfpage 0246 400 300 100 0 200 mbd111 - 1 v (v) vcoin f vco (hz) frequency frequency 4.5 v 5.5 v v = cc 0246 30 10 0 20 mbd112 v (v) vcoin f vco (mhz) 5.5 v 4.5 v v = cc 0246 30 10 0 20 mbd113 v (v) vcoin f vco (khz) 5.5 v 4.5 v v = cc
1999 jan 11 24 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.24 definition of vco frequency linearity: d v = 0.5 v over the v cc range. mga937 - 1 f max f 1 min 1/2v cc f' c f c f 2 v vcoin v v f c f 1 f 2 + 2 -------------- - = linearity f c f c C f c --------------- - 100% = fig.25 frequency linearity as a function of r1, c1 and v cc . 4 4 0 1 mbd114 10 10 2 10 3 8 f vco (%) r1 (k w ) c1 = 1 m f 4.5 v 5.5 v c1 = 39 pf 4.5 v 5.5 v r2 = and d v = 0.5 v. fig.26 power dissipation as a function of component values. 300 0 100 mbd121 10 1 1 200 10 2 r1 (k w ) 4.5 v c1 = 1 m f 5.5 v c1 = 39 pf 4.5 v c1 = 39 pf 5.5 v c1 = 1 m f cc v = p d (w) r2 = . fig.27 power dissipation as a function of component values. r1 = . 300 0 100 mbd110 10 1 1 200 10 2 r2 (k w ) p 5.5 v c1 = 39 pf cc 5.5 v 4.5 v c1 = 1 m f 4.5 v c1 = 39 pf v = d (w)
1999 jan 11 25 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.28 typical power dissipation. 10 3 mbd109 10 2 10 10 4 p dem (w) r (k w ) s v = cc 5.5 v 4.5 v 10 5 10 3 application information this information is a guide for the approximation of values of external components to be used with the 74hct9046a in a phase-locked-loop system. values of the selected components should be within the rages shown in table 2. table 2 survey of components. component value r1 between 3 k w and 300 k w r2 between 3 k w and 300 k w r1 + r2 parallel value >2.7 k w c1 >40 pf table 3 design considerations for vco section. subject phase comparator design consideration vco frequency without extra offset pc1, pc2 vco frequency characteristic with r2 = and r1 within the range 3 k w< r1 < 300 k w , the characteristics of the vco operation will be as shown in fig.29a. (due to r1, c1 time constant a small offset remains when r2 = ). pc1 selection of r1 and c1 given f c , determine the values of r1 and c1 using fig.31. pc2 given f max and f c determine the values of r1 and c1 using fig.31; use fig.33 to obtain 2f l and then use this to calculate f min . vco frequency with extra offset pc1, pc2 vco frequency characteristic with r1 and r2 within the ranges 3 k w< r1 < 300 k w< r2 < 300 k w , the characteristics of the vco operation is as shown in fig.29b. pc1, pc2 selection of r1, r2 and c1 given f c and f l determine the value of product r1c1 by using fig.33. calculate f off from the equation f off = f c - 1.6f l . obtain the values of c1 and r2 by using fig.32. calculate the value of r1 from the value of c1 and the product r1c1. pll conditions with no signal at the sig in input pc1 vco adjusts to f c with f pcin = 90 and v vcoin = 1 2 v cc . pc2 vco adjusts to f offset with f pcin = - 360 and v vcoin = minimum.
1999 jan 11 26 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a 0.6f l f off f vco f max f c f min 1.1 v 1/2v cc v cc 1.1 v v cc vco in 2f l due to r1,c1 due to r2,c1 mga939 - 1 mga938 - 1 f vco f max f c f min 1.1 v 1/2v cc v cc 1.1 v v cc vco in 2f l due to r1,c1 fig.29 frequency characteristic of vco. a. operating without offset; f c = centre frequency; 2f l = frequency lock range. b. operating with offset; f c = centre frequency; 2f l = frequency lock range. b. a.
1999 jan 11 27 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a filter design considerations for pc1 and pc2 of the hct9046a figure 30 shows some examples of passive and active filters to be used with the phase comparators of the hct9046a. transfer functions of phase comparators and filters are given in table 4. table 4 transfer functions of phase comparators and ?lters. phase comparator fig.30 filter type transfer function explanation pc1 a. passive ?lter without damping b. passive ?lter with damping t 1 = r3 c2; t 2 = r4 c2; t 3 = r4 c3; a = 10 5 = dc gain amplitude c. active ?lter with damping pc2 d. passive ?lter with damping a = 10 5 = limit dc gain t 1 = r3' c2; t 2 = r4 c2; t 3 = r4 c3; r3' = r b /17; r b = 25 to 250 k w e. active ?lter with damping a = 10 5 = dc gain amplitude f j w () 1 1j wt 1 + -------------------- - = k pc1 v cc p ---------- - vr = f j w () 1j wt 2 + 1j wt 1 t 2 + () + --------------------------------------- - = f j w () 1j wt 2 + 1a j wt 1 + ---------------------------- - = 1j wt 2 + j wt 1 -------------------- - ? f j w () 1j wt 2 + 1a j wt 1 + ---------------------------- - = 1j wt 2 + j wt 1 -------------------- - ? k pc2 5 4 p ------ - vr = f j w () 1j wt 2 + 1a j wt 1 + ---------------------------- - = 1j wt 2 + j wt 1 -------------------- - ?
1999 jan 11 28 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mbd107 - 1 x 1/ t r3 c2 f (j w ) r3 c2 c3 r4 c3 a r4 c2 r3 r3' c2 r4 ar3' a c3 r4 c2 o t x 2 1 t 1 t 2 o t x 2 1/ t 2 1/ t 3 1/ o t x 2 1/ a t 1/ 1 o t x 2 1/ a t 1/ 1 a 1/ t 2 1/ t 3 1/ t 1 a a 1/ t 2 1/ t 3 t 1 1/a a 1/ t 2 1/ t 3 circuit amplitude characteristic pole zero diagram 1/ t 1 1 t 1 t 2 1/ 1/ t 1 a pc2 pc1 t 1 1/a r3' 1/ f (j w ) fig.30 passive and active filters for hct9046a. a. b. c. d. e.
1999 jan 11 29 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a general design consideration. subject phase comparator design consideration pll locks on harmonics at centre frequency pc1 yes pc2 no noise rejection at signal input pc1 high pc2 low ac ripple content when pll is locked pc1 f r = 2f i ; large ripple content at f pcin = 90 pc2 f r = f i ; small ripple content at f pcin = 0
1999 jan 11 30 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.31 typical value of vco centre frequency (f c ) as a function of c1. 10 7 10 5 10 4 10 3 10 1 10 5 10 3 10 10 2 10 4 10 6 10 6 c1 (pf) 10 7 10 8 (hz) f c 10 2 mbd103 - 1 v = cc 5.5 v 4.5 v w r1 = 3 k r1 = 10 k w r1 = 150 k w r1 = 300 k w 5.5 v 4.5 v 5.5 v 4.5 v 5.5 v 4.5 v r2 = ; v vcoin = 1 2 v cc ; inh = gnd; t amb = 25 c.
1999 jan 11 31 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.32 typical value of frequency offset as a function of c1. 10 7 10 5 10 4 10 3 10 1 10 5 10 3 10 10 2 10 4 10 6 10 6 c1 (pf) 10 7 10 8 (hz) f off 10 2 mbd104 r2 = 150 k w r2 = 300 k w r2 = 3 k w r2 = 10 k w v = cc 4.5 v - 5.5 v 4.5 v - 5.5 v 4.5 v - 5.5 v 4.5 v - 5.5 v r1 = ; v vcoin = 1 2 v cc ; inh = gnd; t amb = 25 c.
1999 jan 11 32 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a fig.33 typical frequency lock range 2f l as a function of the product r1 and c1. v vcoin = 1.1 to (v cc - 1.1) v. k v 2f l v vcoin range ------------------------------------- 2 p rs v () = 10 7 10 5 10 3 10 10 2 10 4 10 6 r1c1 (s) 10 7 10 8 (hz) 2f l mbd105 - 1 v = cc 10 6 10 5 10 4 10 3 10 2 10 1 1 5.5 v 4.5 v
1999 jan 11 33 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a pll design example the frequency synthesizer used in the design example shown in fig.34 has the following parameters: output frequency: 2 mhz to 3 mhz. frequency steps: 100 khz. settling time: 1 ms. overshoot: <20%. the open loop gain is: h (s) g (s) = k p k f k o k n and the closed loop: where: k p = phase comparator gain k f = low-pass filter transfer gain k o = k v /s vco gain k n = 1 n divider ratio. the programmable counter ratio k n can be found as follows: the vco is set by the values of r1, r2 and c1; r2 = 10 k w (adjustable). the values can be determined using the information in table 3. with f c = 2.5 mhz and f l = 500 khz this gives the following values (v cc = 5.0 v): r1 = 30 k w . r2 = 30 k w . c1 = 100 pf. the vco gain is: f u f i ------ - k p k f k o k n 1k p k f k o k n + ----------------------------------------------------- - = n min f out f step ----------- - 2mhz 100 khz --------------------- - 20 == = n max f out f step ----------- - 3mhz 100 khz --------------------- - 30 == = k v 2f l 2 p v cc 1.1 C () 1.1 C ---------------------------------------------- 1mhz 2.8 ---------------- - 2 p 2.24 10 6 rs v ? == the gain of the phase comparator pc2 is: using pc2 with the passive filter as shown in fig.34 results in a high gain loop with the same performance as a loop with an active filter. hence loop filter equations as for a high gain loop should be used. the current source output of pc2 can be simulated then with a fictive filter resistance: the transfer functions of the filter is given by: where: t 1 = r3' c2. t 2 = r4 c2. the characteristic equation is: this results in: or: this can be written as: with the natural frequency w n defined as: and the damping value given as: in fig.35 the output frequency response to a step of input frequency is shown. the overshoot and settling time percentages are now used to determine w n . from fig.35 it can be k p 5 4 p ------------ 0.4v r == r3' r b 17 ------ - = k f 1s t 2 + s t 2 ------------------ = 1k p k f k o k n + 1k p 1s t 2 + s t 1 ------------------ ? ? ?? k v s ----- - k n 0 = + s 2 sk p k v k n t 2 t 1 ---- - k p k v k n t 1 0 = ++ s 2 2 zw n s w n () 2 + + 0 = w n k p k v k n t 1 -------------------------------- = z 0.5 t 2 w n = seen that the damping ratio z = 0.707 will produce an overshoot of less than 20% and settle to within 5% at w n t = 5. the required settling time is 1 ms. this results in: rewriting the equation for natural frequency results in: the maximum overshoot occurs at n max = 30; hence k n = 1 30 : when c2 = 470 nf, it follows: hence the current source bias resistance r b = 17 2550 = 43 k w . with z = 0.707 (0.5 t 2 w n ) it follows: for extra ripple suppression a capacitor c3 can be connected in parallel with r4, with an extra t 3 =r4 c3. for stability reasons t 3 should be < 0.1 t 2 , hence c3 < 0.1c2, or c3 = 39 nf. w n 5 t -- - 5 0.001 -------------- - 510 3 rs == = t 1 k p k v k n w n () 2 -------------------------------- = t 1 0.4 2.24 10 6 5000 2 30 ----------------------------------------- - 0.0012 == r3' t 1 c2 ------- - 0.0012 470 10 9 C --------------------------- - 2550 == = t 2 0.707 0.5 5000 --------------------------- - 0.00028 == r4 t 2 c2 ------- - 0.00028 470 10 9 C --------------------------- - 600 w == =
1999 jan 11 34 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mbd098 r4 c2 r2 r1 vco r3' phase comparator pc2 divide by 10 "190" oscillator "hcu04" 13 100 khz 14 3 4 f out programmable divider "4059" 9 11 12 6 7 5 1 mhz k p k n k f k o c1 c3 (1) r 15 b f u fig.34 frequency synthesizer. r1 = 30 k w . r2 = 30 k w . c1 = 100 pf. r3 ' = 2550 w . r b = 43 k w . r4 = 600 w . c2 = 470 nf. c3 = 39 nf. (1) r3' fictive resistance = r3' r b 17 ------ - = 012 4 1.6 1.0 0.6 0 0.8 mga959 3 1.4 1.2 0.4 0.2 5678 w n t dw (t) e dw e / w n df (t) e df e / w n - 0.6 0 0.4 1.0 0.2 - 0.4 - 0.2 0.6 0.8 = 5.0 z 0.5 0.707 1.0 = 0.3 z = 2.0 z fig.35 type 2, second order frequency step response.
1999 jan 11 35 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a mga952 3.1 3.0 2.9 2.1 2.0 1.9 0 0.5 1.0 1.5 2.0 2.5 time (ms) proportional to output frequency (mhz) n = 30 n stepped from 29 to 30 step input n stepped from 21 to 20 fig.36 frequency compared to the time response. since the output frequency is proportional to the vco control voltage, the pll frequency response can be observed with an oscilloscope by monitoring pin 9 of the vco. the average frequency response, as calculated by the laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple rc filter, whose time constant is long compared with the phase detector sampling rate but short compared with the pll response time. further information for an extensive description and application example please refer to application note ordering number 9398 649 90011. also available a computer design program for plls ordering number 9398 961 10061.
1999 jan 11 36 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a package outlines unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 92-10-02 95-01-19 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.10 0.020 0.19 050g09 mo-001ae m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
1999 jan 11 37 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1999 jan 11 38 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a soldering introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. through-hole mount packages s oldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. surface mount packages r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 jan 11 39 philips semiconductors product speci?cation pll with bandgap controlled vco 74hct9046a suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. mounting package soldering method wave reflow (1) dipping through-hole mount dbs, dip, hdip, sdip, sil suitable (2) - suitable surface mount bga, sqfp not suitable suitable - hlqfp, hsqfp, hsop, htssop, sms not suitable (3) suitable - plcc (4) , so, soj suitable suitable - lqfp, qfp, tqfp not recommended (4)(5) suitable - ssop, tssop, vso not recommended (6) suitable - data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 489 4339/4239, fax. +30 1 481 4240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 printed in the netherlands 245002/00/03/pp40 date of release: 1999 jan 11 document order number: 9397 750 05007

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